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May 1997
ML2252*, ML2259** P Compatible 8-Bit A/D Converters with 2- or 8-Channel Multiplexer
GENERAL DESCRIPTION
The ML2252 and ML2259 combine an 8-bit A/D converter, 2- or 8-channel analog multiplexer, and a microprocessor compatible 8-bit parallel interface and control logic in a single monolithic CMOS device. Easy interface to microprocessors is provided by the latched and decoded multiplexer address inputs and a double buffered three-state data bus. These analog-todigital converters allow the microprocessor to operate completely asynchronous to the converter clock. The built in sample and hold function provides the ability to digitize a 5V, 50kHz sinewave to 8-bit accuracy. The differential comparator design provides low power supply sensitivity to DC and AC variations. The voltage reference can be externally set to any value between ground and VCC, thus allowing a full conversion over a relatively small span. All parameters are guaranteed over temperature with a power supply voltage of 5V 10%. The device is suitable for a wide range of applications from process and machine control to consumer, automotive, and telecommunication applications.
FEATURES
s s s s s s s s s s s s s
Conversion time (fCLK = 1.46MHz); 6.6s Total unadjusted error; 1/2LSB or 1LSB No missing codes Sample and hold; 390ns acquisition Capable of digitizing a 5V, 50kHz sinewave 2- or 8-channel input multiplexer 0V to 5V analog input range with single 5V power supply Operates ratiometrically or with up to 5V voltage reference No zero or full scale adjust required Analog input protection; 25mA per input min Continuous conversion mode Low power dissipation; 15mW max TTL and CMOS compatible digital inputs and outputs
ML2252 BLOCK DIAGRAM
* This Part Is Obsolete ** This Part Is End of Life As Of August 1, 2000
VCC CH0 2-CHANNEL MULTIPLEXER
CLOCK CONTROL & TIMING
START EOC
CH1
+
-
8pF
+ COMP -
DB0 SUCCESSIVE APPROXIMATION REGISTER THREE STATE OUTPUT BUFFER D/A CONVERTER DB1 DB2 DB3 DB4 DB5 DB6 DB7
ADDRESS LATCH AND DECODER ALE A0
8pF
A/D WITH SAMPLE-AND-HOLD FUNCTION GND
+VREF
-VREF
OE
1
ML2252, ML2259
ML2259 BLOCK DIAGRAM
VCC CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 8pF 8-CHANNEL MULTIPLEXER + CONTROL & TIMING CLK START EOC
-
DB0 + COMP - SUCCESSIVE APPROXIMATION REGISTER THREE STATE OUTPUT BUFFER D/A CONVERTER DB1 DB2 DB3 DB4 DB5 DB6 DB7
ADDRESS LATCH AND DECODER ALE A0 A1 A2
8pF
A/D WITH SAMPLE-AND-HOLD FUNCTION GND
+VREF
-VREF
OE
PIN CONFIGURATION
ML2252 20-Pin DIP (P20)
CH1 START EOC DB3 OE CLK VCC +VREF GND DB1
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
ML2252 20-Pin PLCC (Q20)
ADDR0 19 18 17 16 15 14 9 GND 10 11 DB1 DB2 12 -VREF 13 DB0 ALE DB7 DB6 DB5 DB4
CH1
START
CH1 1
CH3
CH0 ADDR0 ALE DB7 DB6 DB5 DB4 DB0 -VREF DB2
3 DB3 OE CLK VCC +VREF 4 5 6 7 8
2
20
TOP VIEW
TOP VIEW
ML2259 28-Pin DIP(P28W)
CH3 CH4 CH5 CH6 CH7 START EOC DB3 OE CLK VCC +VREF GND DB1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
ML2259 28-Pin PLCC (Q28)
CH6 CH5 CH4 CH2 CH2 CH1 CH0 ADDR0 ADDR1 ADDR2 ALE DB7 DB6 DB5 DB4 DB0 -VREF DB2 CH0
4 CH7 START EOC DB3 OE CLK VCC 5 6 7 8 9 10 11 12
+VREF
3
2
1
28
CH0
EOL
27
26 25 24 23 22 21 20 19 18
DB4
ADDR0 ADDR1 ADDR2 ALE DB7 DB6 DB5
13 14
GND DB1
15
DB2
16
-VREF
17
DB0
TOP VIEW
TOP VIEW
2
ML2252, ML2259
PIN DESCRIPTION
Pin Number ML2252 ML2259 1 2 3 4 5 6 7 Name CH3 CH4 CH5 CH6 CH7 START EOC Function Analog input 3. Analog input 4. Analog input 5. Analog input 6. Analog input 7. Start of conversion. Active high digital input pulse initiates conversion. End of conversion. This output goes low after a START pulse occurs, stays low for the entire A/D conversion, and goes high after conversion is completed. Data on DB0-DB7 is valid on rising edge of EOC and stays valid until next EOC rising edge. Data output 3. Output enable input. When OE = 0, DB0-DB7 are in high impedance state; OE = 1, DB0-DB7 are active outputs. Clock. Clock input provides timing for A/D converter, S/H, and digital interface. Positive supply. 5V 10%. Positive reference voltage. Ground. 0V, all analog and digital inputs or outputs are referenced to this point. Data output 1. Data output 2. Negative reference voltage. Data output 0. Data output 4. Data output 5. Data output 6. Data output 7. Address latch enable. Input to latch in the digital address (ADDR2-0) on the rising edge of the multiplexer. Address input 2 to multiplexer. Digital input for selecting analog input. Address input 1 to multiplexer. Digital input for selecting analog input. Address input 0 to multiplexer. Digital input for selecting analog input. Analog input 0. Analog input 1. Analog input 2.
2 3
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
DB3 OE CLK VCC +VREF GND DB1 DB2 -VREF DB0 DB4 DB5 DB6 DB7 ALE ADDR2 ADDR1 ADDR0 CH0 CH1 CH2
19 20 1
3
ML2252, ML2259
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Voltage, VCC .............................................................. 6.5V Logic Inputs ....................................... -0.3V to VCC 0.3V Analog Inputs ..................................... -0.3V to VCC 0.3V Input Current per Pin ............................................ 25mA Storage Temperature ................................ -65C to 150C Lead Temperature (Soldering 10 sec.) .................... 260C Thermal Resistance (qJA) 20-Pin PDIP ..................................................... 67C/W 20-Pin PLCC .................................................... 78C/W 28 Pin PDIP ..................................................... 48C/W 28-Pin PLCC .................................................... 68C/W
OPERATING CONDITIONS
Supply Voltage, VCC .............................................. 4.5V to 6.3V Temperature Range ........................................ 0C to 70C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = +VREF = 5V 10%, -VREF = GND, fCLK = 1.46MHz, TA = Operating temperature range (Note 1)
ML2252B, ML2259B PARAMETER CONDITIONS MIN TYP MAX MIN ML2252C, ML2259C TYP MAX UNITS
Converter and Multiplexer Characteristics Total Unadjusted Error +VREF Voltage Range -VREF Voltage Range Reference Input Resistance Analog Input Range Power Supply Sensitivity (Note 3) DC, VCC = 5V 10% 100mVp-p, 100kHz Sine on VCC, VIN = 0 IOFF, Off Channel Leakage Current (Note 9) On Channel = VCC, (Note 4) Off Channel = 0V On Channel = 0V, (Note 4) Off Channel = VCC ION, On Channel Leakage Current (Note 9) On Channel = 0V, (Note 4) Off Channel = VCC On Channel = VCC, (Note 4) Off Channel = 0V -1 1 -1 1 -1 1 VREF = VCC, (Note 2) -VREF GND - 0.1 14 GND - 0.1 1/32 1/16 -1 1 20 1/2 VCC + 0.1 +VREF 35 -VREF GND - 0.1 14 20 1 VCC + 0.1 +VREF 28 VCC + 0.1 1/32 1/16 1/4 LSB V V ky V LSB LSB A A A A
VCC + 0.1 GND - 0.1 1/4
SYMBOL Digital and DC VIN(1) VIN(0) IIN(1) IIN(0) VOUT(1) VOUT(0) IOUT ICC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Input Current Logical "0" Input Current Logical "1" Output Voltage Logical "0" Output Voltage Three-State Output Current VIN = VCC VIN = 0V IOUT = -2mA IOUT = 2mA VOUT = 0V VOUT = VCC Supply Current
2.0 0.8 1 -1 4.0 0.4 -1 1 1.5 3
V V A A V V A A mA
4
ML2252, ML2259
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
(Continued)
CONDITIONS MIN TYP MAX UNITS
AC and Dynamic Performance Characteristics (Note 5) tACQ fCLK tC SNR Sample and Hold Acquisition Clock Frequency Conversion Time Signal to Noise Ratio VIN = 51kHz, 5V sine. fCLK = 1.46MHz (fSAMPLING > 150kHz). Noise is sum of all nonfundamental components up to 1/2 of fSAMPLING VIN = 51kHz, 5V sine. fCLK = 1.46MHz (fSAMPLING > 150kHz). THD is sum 2, 3, 4, 5 harmonics relative to fundamental VIN = fA + fB. fA = 49kHz, 2.5V sine. fB = 47.8kHz, 2.5V sine, fCLK = 1.46MHz (fSAMPLING > 150kHz). IMD is (fA + fB), (fA - fB), (2fA + fB), (2fA - fB), (fA + 2fB), (fA - 2fB) relative to fundamental VIN = 0 to 50kHz. 5V sine relative to 1kHz (Note 6) 40 1/2 50 Synchronous only, (Note 7) 40 50 0 50 Figure 1, CL = 50pF Figure 1, CL = 10pF t1H, 0H CIN COUT Output Disable for DB0-DB7 Figure 1, CL = 50pF Figure 1, CL = 10pF Capacitance of Logic Input Capacitance of Logic Outputs 5 10 100 50 100 50 10 8.5 47 1/2 1460 8.5 + 250ns 1/fCLK kHz 1/fCLK dB
THD
Total Harmonic Distortion
-60
dB
IMD
Intermodulation Distortion
-60
dB
FR tDC tEOC tWS tSS tWALE tS tH tH1, H0
Frequency Response Clock Duty Cycle End of Conversion Delay Start Pulse Width Start Pulse Setup Time Address Latch Enable Pulse Width Address Setup Address Hold Output Enable for DB0-DB7
0.1 60 1/2 + 250ns
dB % 1/fCLK ns ns ns ns ns ns ns ns ns pF pF
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Total unadjusted error includes offset, full scale, linearity, multiplexer and sample and hold errors. Note 3: For -VREF * VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct -- especially at elevated temperatures, and cause errors for analog inputs near full scale. The spec allow 100mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 100mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of 4.900VDC over temperature variations, initial tolerance and loading. Note 4: Leakage current is measured with the clock not switching. Note 5: CL = 50pF, timing measured at 50% point. Note 6: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the minimum time the clock is high or the minimum time the clock is low must be at least 40ns. The maximum time the clock can be high or low is 60s. Note 7: The conversion start setup time requirement only needs to be satisfied if a conversion must be synchronized to a given clock rising edge. If the setup time is not met, start conversion will have an uncertainty of one clock pulse.
5
ML2252, ML2259
tf DATA OUTPUT CL 10k VOH OUTPUT GND OUTPUT ENABLE VCC GND 50% 10% t1H 90% 90% 90% tr 50% 10% t0H 50%
VCC 10k DATA OUTPUT CL OUTPUT VOL OUTPUT ENABLE VCC GND VCC 50% 10%
tf 90% 90%
tr 50% 10% tH0 50%
t0H 10%
Figure 1. High Impedance Test Circuits and Waveforms
TYPICAL PERFORMANCE CURVES
1.0 VCC = 5V VREF = 5V 0.75
LINEARITY ERROR (LSB)
0.5
0.25 25C
0 0.001
0.01 0.1 CLOCK FREQUENCY (MHz)
1.0
Figure 2. Linearity Error vs fCLK
6
ML2252, ML2259
TYPICAL PERFORMANCE CURVES (Continued)
1 VCC = 5V fCLK = 1.46MHz 0.75
2 VCC = 5V VIN = 0V fCLK = 1.46MHz TA = 25C
1.5 OFFSET ERROR (LSB)
LINEARITY ERROR (LSB)
0.5 25C
1
0.25
0.5
0 0 1 2 VREF (VDC) 3 4 5
0 0 1 2 VREF (VDC) 3 4 5
Figure 3. Linearity Error vs VREF Voltage
Figure 4. Unadjusted Offset Error vs VREF Voltage
1.0 FUNCTIONAL DESCRIPTION
1.1 MULTIPLEXER ADDRESSING The ML2252 and ML2259 contain a single ended analog multiplexer. A particular input channel is selected by using the address decoder. The relationship between the address inputs, ADDR0-ADDR2, and the analog input selected is shown in Table 1. The address inputs are latched into the decoder on the rising edge of the address latch signal ALE. ML2252
SELECTED ANALOG CHANNEL ADDRESS INPUT
1.2 A/D CONVERTER The A/D converter uses successive approximation to perform the conversion. The converter is composed of the successive approximation register, the DAC and the comparator. The DAC generates the precise levels that determine the linearity and accuracy of the conversion. The DAC is composed of a capacitor upper array and a resistor lower array. The capacitor upper array generates the 4 MSB decision levels while the series resistor lower array generates the 4 LSB decision levels. A switch decoder tree is used to decode the proper level from both arrays. The capacitor/resistor array offers fast conversion, superior linearity and accuracy since matching is only required between 24 = 16 elements (as opposed to 28 = 256 elements in conventional designs). And since the levels are based on the ratio of capacitors to capacitors and resistors to resistors, the accuracy and long term stability of the converter is improved. This also guarantees monotonicity and no missing codes, as well as eliminating any linearity temperature or power supply dependence. The successive approximation register is a digital block used to store the bit decisions from the conversion. The comparator design is unique in that it is fully differential and auto zeroed. The fully differential architecture provides excellent noise immunity, excellent power supply rejection, and wide common mode range. The comparator is auto zeroed at the start of each conversion in order to remove any DC offset and full scale gain error, thus improving accuracy and linearity.
CH0 CH1 ML2259
SELECTED ANALOG CHANNEL CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
0 1
ADDRESS INPUT ADDR2 ADDR1 ADDR0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Table 1. Multiplexer Address Decoding
7
ML2252, ML2259
Another advantage of the capacitor array approach used in the ML2252 and ML2259 is the inherent sample-and-hold function. This true S/H allows an accurate conversion to be done on the input even if the analog signal is not stable. Linearity and accuracy are maintained for analog signals up to 1/2 the sampling frequency. As a result, input signals up to 50kHz can be converted without degradation in linearity or accuracy. The sequence of events during a conversion is shown in figure 5. The rising edge of a START pulse resets the internal registers and initiates a conversion on the next rising edge of CLK providing that (tSS) start pulse setup time is satisfied. If this setup time is not met, start conversion will have an uncertainty of one clock pulse. The input is then sampled for the next half CLK period until EOC goes low. EOC goes low on the falling edge of the next CLK pulse indicating that the conversion is now beginning. The actual conversion now takes place for the next eight CLK pulses, one bit for each CLK pulse. After the conversion is done, the data is updated on DB0-DB7 and EOC goes high on the rising edge of the 9th CLK pulse, indicating that the conversion has been completed and data is valid on DB0-DB7. The data will stay valid on DB0-DB7 until the next conversion updates the data word on the next rising edge of EOC. A conversion can be interrupted and restarted at any time by a new START pulse. 1.3 ANALOG INPUTS AND SAMPLE/HOLD The ML2252 and ML2259 have a true sample-and-hold circuit which samples both the selected input and ground simultaneously. These analog to digital converters can reject AC common mode signals from DC-50kHz as well as maintain linearity for signals from DC-50kHz. The plot in Figure 6 shows a 2048 point FFT of the ML2259 converting a 50kHz, 0 to 5V, low distortion sine wave input. The ML2252 and ML2259 sample and digitize, at their specified accuracy, dynamic input signals with frequency components up to the Nyquist frequency (one-half the sampling rate). The output spectra yields precise measurements of input signal level, harmonic components, and signal to noise ratio up to the 8-bit level. The near ideal signal to noise ratio is maintained independent of increasing analog input frequencies to 50kHz. The signal at the analog input is sampled during the interval when the sampling switch is open prior to conversion start. The sampling window (S/H acquisition time) is one half CLK period long and occurs one half CLK period after START goes low. When the sampling switch closes at the start of the S/H acquisition time, 8pF of capacitance is thrown onto the analog input. One half CLK period later, the sampling switch opens, the signal present at analog input is stored and conversion starts. Since any error on the analog input at the end of the S/H acquisition time will cause additional conversion error, care should be taken to insure adequate settling and charging time from the source. If more charging or settling time is needed to reduce these analog input errors, a longer CLK period can be used. Each analog input has dual diodes to the supply rails, and a minimum of 25mA (100mA typically) can be injected into each analog input without causing latchup.
1/fCLK CLK tSS START tWS ALE tWALE ADDR0-ADDR2 tS EOC tC DB0-DB7 PREVIOUS DATA DATA tHI, tHO tIH, tOH OE tH tEOC 1 2 3 4 5 6 7 8 9
Figure 5. Timing Diagram
8
ML2252, ML2259
1.4 REFERENCE The voltage applied to the +VREF and -VREF inputs defines the voltage span of the analog input (the difference between VINMAX and VINMIN) over which the 256 possible output codes apply. The devices can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pins must be connected to a voltage source capable of driving the reference input resistance, typically 20k. In a ratiometric system, the analog input voltage is proportional to the voltage used for the A/D reference. This voltage is typically the system power supply, so the +VREF pin can be tied to VCC and -VREF tied to GND. This technique relaxes the stability requirements of the system reference as the analog input and A/D reference move together maintaining the same output code for a given input condition. For absolute accuracy, where the analog input varies between specific voltage limits, the reference pins can be biased with a time and temperature stable voltage source. +VREF and -VREF can be at any voltage between VCC and GND. In addition, the difference between +VREF and -VREF can be set to small values for conversions over smaller voltage ranges. Particular care must be taken with regard to noise pickup, circuit layout ond system error voltage sources when operating with a reduced span due to the increased sensitivity converter. 1.5 POWER SUPPLY AND REFERENCE DECOUPLING A 10F electrolytic capacitor is recommended to bypass VCC to GND, using as short a lead length as possible. In addition, with clock frequencies above 1MHz, a 0.1F ceramic disc capacitor should be used to bypass VCC to GND. If REF+ and REF- inputs are driven by long lines, they should be bypassed by 0.1F ceramic disc capacitors at the reference input pins (pins 12, 16). 1.6 DYNAMIC PERFORMANCE Signal-to-Noise Ratio Signal-to-noise ratio (SNR) is the measured signal to noise at the output of the converter. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency. SNR is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical SNR for a sine wave is given by SNR = (6.02N + 1.76)dB where N is the number of bits. Thus for ideal 8-bit converter, SNR = 49.92dB. Harmonic Distortion Harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. Total harmonic distortion (THD) of the ML2252 and ML2259 are defined as 20log
1/ 2 (V2 + V3 + V4 + V5 ) V1 2 2 2 2
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 are the rms amplitudes of the individual harmonics.
0 -10 -20 -30
MAGNITUDE (dB)
-40 -50 -60 -70 -80 -90 -100 -110 37.5 FREQUENCY (kHz) 75
Figure 6. Output Spectrum
9
ML2252, ML2259
Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fA and fB, any active device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfA + nfB, where m, n = 0, 1, 2, 3,... . Intermodulation terms are those for which m or n is not equal to zero. The (IMD) intermodulation distortion specification includes the second order terms (fA + fB) and (fA - fB) and the third order terms (2fA + fB), (2fA - fB), (fA + 2fB) and (fA - 2fB) only. 1.7 DIGITAL INTERFACE The analog inputs are selected by the digital addresses, ADDR0-ADDR2, and latched on the rising edge of ALE. This is described in the Multiplexer Addressing section. A conversion is initiated by the rising edge of a START pulse. As long as this pulse is high, the internal logic is reset. The sampling interval starts with the following CLK rising edge after a START falling edge and ends on the falling edge of CLK. The conversion starts and EOC goes low. The sampling clock is at least one half CLK period wide. Each bit conversion in the successive approximation process takes 1 CLK period. On the rising edge of the ninth CLK pulse, the digital output of the conversion is updated on the outputs DB0-DB7 and EOC goes high indicating the conversion is done and data on DB0-DB7 is valid. One feature of the ML2252 and ML2259 is that the data is double buffered. This means that the outputs DB0-DB7 will stay valid until updated at the end of the next conversion and will not become invalid when the next conversion starts. This facilitates interfacing with external logic of P. The signal OE drives the data bus, DB0-DB7, into the high impedance state when held low. This allows the ML2252 and ML2259 to be tied directly to a P system bus without any latches or buffers. 1.7.1 Restart During Conversion If the A/D is restarted (start goes low and returns high) during a convesion, the converter is reset and a new conversion is started. The output data latch is not updated if the conversion in process is not allowed to be completed. EOC will remain low and the output data latch is not updated. 1.7.2 Continuous Conversions In the free-running, continuous conversion mode, the start input is tied to the (figure 7) EOC output. An initialization pulse, following power-up, of mementarily forcing a logic high level is required to guarantee operation.
VCC START
ML2252 ML2259
EOC START
Figure 7. Continuous Conversion Mode
2.0 TYPICAL APPLICATIONS
VCC (5VDC)
4k
15VDC + - -15VDC 600
VCC
1k FS ADJ
- + 0.85VCC +VREF VCC + 10F
ANALOG IN
VCC +
24k
ML2252 ML2259
CH
ML2252 ML2259
GND
10F
XDR 20k - 1k ZERO ADJ 3k -VREF + 0.15VCC
Figure 8. Protecting the Input
Figure 9. Operating with Ratiometric Transducers 15% of VCC - VXDR - 85% of VCC
10
ML2252, ML2259
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P20 20-Pin PDIP
1.010 - 1.035 (25.65 - 26.29) 20
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26)
0.060 MIN (1.52 MIN) (4 PLACES)
1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: Q20 20-Pin PLCC
0.385 - 0.395 (9.78 - 10.03) 0.350 - 0.356 (8.89 - 9.04) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS)
0.042 - 0.048 (1.07 - 1.22)
6
PIN 1 ID
16
0.350 - 0.356 (8.89 - 9.04)
0.385 - 0.395 (9.78 - 10.03)
0.200 BSC (5.08 BSC)
0.290 - 0.330 (7.36 - 8.38)
11 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.19 - 4.57) 0.146 - 0.156 (3.71 - 3.96) 0.009 - 0.011 (0.23 - 0.28) 0.100 - 0.110 (2.54 - 2.79)
0.013 - 0.021 (0.33 - 0.53) SEATING PLANE
11
ML2252, ML2259
PHYSICAL DIMENSIONS
inches (millimeters) (Continued)
Package: P28W 28-Pin Wide PDIP
1.440 - 1.460 (36.57 - 37.09) 28
PIN 1 ID
0.530 - 0.550 0.595 - 0.625 (13.46 - 13.97) (15.11 - 15.88)
0.070 MIN (1.77 MIN) (4 PLACES)
1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.190 MAX (4.83 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: Q28 28-Pin PLCC
0.485 - 0.495 (12.32 - 12.57) 0.450 - 0.456 (11.43 - 11.58) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS)
0.042 - 0.048 (1.07 - 1.22)
PIN 1 ID 8 22 0.450 - 0.456 0.485 - 0.495 (11.43 - 11.58) (12.32 - 12.57) 0.300 BSC (7.62 BSC) 0.390 - 0.430 (9.90 - 10.92)
15 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.009 - 0.011 (0.23 - 0.28)
0.099 - 0.110 (2.51 - 2.79)
0.013 - 0.021 (0.33 - 0.53)
SEATING PLANE
12
ML2252, ML2259
ORDERING INFORMATION
TOTAL UNADJUSTED ERROR TEMPERATURE RANGE
PART NUMBER
PACKAGE
Two Analog Inputs, 20-Pin Package ML2252BCP (OBS) ML2252BCQ (OBS) ML2252CCP (OBS) ML2252CCQ (OBS) 1/2 LSB 1 LSB 0C to 70C 0C to 70C 0C to 70C 0C to 70C Molded DIP (P20) Molded PLCC (Q20) Molded DIP (P20) Molded PLCC (Q20)
Eight Analog Inputs, 28-Pin Package ML2259BCP (EOL) ML2259BCQ (OBS) ML2259CCP (OBS) ML2259CCQ (OBS) 1/2 LSB 1 LSB 0C to 70C 0C to 70C 0C to 70C 0C to 70C Molded DIP (Q28) Molded PLCC (Q28) Molded DIP (P28W) Molded PLCC (Q28)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS2252_59-01
13

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Price & Availability of ML2252

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